Description
With semiconductors reaching their limits and unable to follow Moore’s Law, nanoscale vacuum channel devices are receiving significant attention as a potential alternative to next-generation electronics. This is due to their benefits of high-frequency operation, radiation hardness, wide range of thermal operation, and compatibility with CMOS fabrication techniques. While this technology has been extensively explored in gated active switching devices with three or more terminals, these devices are more complex and difficult to fabricate compared to simple two terminal nanoscale vacuum channel diodes (NVCDs). This paper explores the design and fabrication of NVCD large arrays. Additionally, a half-adder circuit is simulated using the NVCD lumped-element unit cell model and corresponding NOR gate developed from experimental data.
To begin with, the NVCD array with 650 devices are fabricated through a combination of electron beam lithography (EBL), metal deposition and liftoff. After fabrication, the current is measured during a voltage sweep from -25 to 25 V providing the IV curve. The IV data is validated via curve fitting to follow Fowler-Nordheim tunnelling in the high voltage regions, and Schottky emission at low voltages. A theoretical model of emission is constructed from these testing results and then combined with COMSOL electrostatic simulations to create a novel lumped-element circuit model of the device.
In combination with discrete components, a NOR logic gate SPICE model circuit is proposed utilising the theoretical emission model in previous work. The NOR gate is chosen due to logical completeness. The proposed NOR gate provides a rail-to-rail voltage output at 0-25 V. Using the previously reported NOR gate, a half-adder circuit is simulated in this work. This functional arithmetic circuit serves as a proof-of-concept for the emerging NVCD technology and as such shows a pathway for fully semiconductor-free nanoscale vacuum channel integrated circuits.
| I am the presenting author | No |
|---|---|
| If you are not the presenting author, please give the presenting author's name: | Deepak Sharma |