Description
Artificial neural networks increasingly rely on large-scale tensor operations that dominate inference latency and energy consumption. Photonic computing offers a promising route toward high-speed acceleration by performing linear algebra directly in the optical domain. Here, we present an integrated, reconfigurable photonic tensor processor for deep neural network inference. The system implements an all-optical intensity-based crossbar architecture in which input vectors and matrix weights are encoded using electro-absorption modulators, while accumulated optical outputs are detected by integrated photodiodes. Since tensor operations are executed by optical propagation through the crossbar, the full operation can be completed within a single clock cycle. This single-cycle computing provides a direct path toward ultra-low-latency inference.
Fabricated in a silicon photonics platform, the processor is driven by a packaged self-injection-locked microcomb that supplies all required optical carriers from a single source. The photonic chip is embedded in a rack-mounted electro-optic system with high-speed electronic input/output and a PyTorch-compatible software interface. Pretrained neural networks are mapped to the photonic hardware through calibration routines that compensate device nonlinearities, inter-channel crosstalk, and wavelength-dependent responses. In addition, hardware-aware fine-tuning adapts the networks to the measured analog noise characteristics of the processor. By incorporating realistic weight and output noise during training, the models become robust against finite precision, stochastic fluctuations, and residual systematic errors inherent to analog computation.
We demonstrate convolutional neural network inference on MNIST and CIFAR-10, achieving 98.1% and 72.0% classification accuracy, respectively. Finally, we give a realistic outlook on system improvements, including reduced optical loss, more stable packaging, larger tensor cores, improved electronic control, and automated calibration. Together with a more integrated electro-optic test bench and simplified interfacing, these steps provide a practical path toward scalable, low-latency optical AI accelerators.
Meyer, L. et al., Nat Commun 17, 3396 (2026). https://doi.org/10.1038/s41467-026-71599-2
| I am the presenting author | Yes |
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