Description
Fault-tolerant quantum computing (FTQC) will require millions of interconnected qubits operating together with high fidelities. Qubits in silicon quantum dots promise high qubit density and integration with on-chip classical control electronics. A key barrier to scaling this technology is device overheating: above 1K, qubit coherence declines significantly. Increased power dissipation in larger devices due to control electronics and microwave drive create strict limits on thermal power budget which limit qubit count. Improving device thermalization in cryogenic experimental setups will increase power budgets and allow for devices with much higher qubit count.
In this work, we characterize on-chip heating both in simulation and experimentally. On-chip thermometry at sub 1-K temperatures is performed using a range of foundry-fabricated silicon devices to extract fundamental material parameters. We investigate heating in 2D and flip-chip 3D integrations, and experiment with various methods designed to improve device thermalization. Decisions in material stack, enclosure geometry and operating conditions result in measurable improvements in on-chip heating. These results inform the design of integrated cryo-CMOS and qubit chips in the near future.
| I am the presenting author | Yes |
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