26th Australian Institute of Physics Congress and the Australian and New Zealand Conference on Optics and Photonics

Benchmarking Streaming Readout Performance of CAEN Digitizer 2.0 Platforms

Not scheduled

20m

Belinda Hutchinson Building (The University of Sydney )

Poster AIP | Nuclear and Particle Physics (NUPP)

Speaker

Mr Yuri Venturini (CAEN S.p.A.)

Description

Modern nuclear and particle physics experiments, medical imaging systems, and large-scale detector readouts demand ever-higher data throughput, driving the adoption of streaming readout (SRO) architectures alongside conventional triggered acquisition. This work presents a systematic performance evaluation of the CAEN Digitizer 2.0 family (x2740/x2745, x2730, and x2751), which combines high-speed Flash ADCs, FPGA-based real-time signal processing, large DDR4 buffers, an embedded ARM processor, and native USB 3.1, 1 GbE TCP, and 10 GbE UDP connectivity. We characterise both triggered and streaming readout paths to identify throughput limitations and saturation behaviour, from the front-end ADC stage to the high-speed network link. Particular attention is devoted to network optimisation: enabling Jumbo Frames (MTU 9000) transmits large UDP datagrams without fragmentation, reducing CPU overhead, minimising packet loss, and improving link efficiency, which is essential to exploit the full 10 GbE UDP bandwidth under sustained streaming. In triggered readout with raw waveform transmission over 10 GbE UDP, the system sustains approximately 1.1 GB/s with no packet loss, a limit set by network bandwidth rather than internal processing. In list-mode streaming readout with onboard digital pulse processing, performance reaches up to about 40 Mcps per board (several Mcps per channel), where the dominant bottleneck is FPGA-level event sorting and handling. When waveform data are added to the streaming payload, the achievable hit rate becomes network-bandwidth constrained. Software benchmarks using the CAEN FELib C library reveal a per-event processing and context-switching bottleneck limiting decoded rates to a few Mcps, while CoMPASS, which adds multi-board synchronisation, event building, and online filtering, exhibits a ceiling near 1 Mcps. These results demonstrate that CAEN Digitizer 2.0 platforms reliably support high-rate SRO applications when properly configured, and identify FPGA event handling and software parallelisation as clear targets for future improvement.