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Description
The Circular Electron Positron Collider (CEPC) is proposed for Higgs boson studies and will employ Silicon Photomultipliers (SiPMs) extensively in calorimeter detectors. This work presents SIPAC, a dedicated SiPM readout ASIC for calorimeters, implemented in a 55-nm CMOS process. To accommodate the relatively slow SiPM signals after crystal conversion, a voltage amplifier is adopted as the front-end architecture. Considering the strong influence of electronic noise on timing and energy resolution, dedicated shaping circuits are designed for parallel energy and timing measurements.
The energy path incorporates a slow shaper with two-stage low-pass filtering, achieving a signal-to-noise ratio (SNR) of 17, while the timing path employs a fast shaper with band-pass filtering. The shaped signals are digitized by a shared SAR ADC and a hybrid TDC, respectively. The TDC combines coarse counting with delay-line-based fine interpolation for time-of-arrival measurement. AC coupling is implemented to isolate the DAC used for SiPM gain adjustment.
Post-layout simulations show that, within an input dynamic range of 1.28 pC to 3.84 nC, the nonlinearity errors are 0.4% and 0.3% for the high-gain and low-gain paths, respectively, while the SAR ADC achieves 10-bit ENOB. A four-channel prototype was fabricated in October 2025 and returned in February 2026. Standalone measurements demonstrate a dynamic range of 3000, integral nonlinearity better than 2% and 1.2% for the high-gain and low-gain channels, respectively, an SNR of 17.65 for minimum-ionizing-particle signals, and a TDC resolution of 102 ps. The results will also be presented in this poster.