Speaker
Description
Future high-energy physics experiments and highly-granulated silicon detectors impose stringent requirements on readout electronics regarding power consumption, footprint, and timing precision. This report presents LATRICi, a pulse-interleaved time-to-digital converter (TDC) implemented in a 55nm CMOS process. As an evolution of the initial LATRIC0 prototype, which utilized an event-driven ring oscillator architecture with a 31-ps resolution, the proposed design optimizes delay cells to mitigate process mismatch, achieving a simulated average unit delay (Td) of 22.5 ps. To enhance timing precision, LATRICi integrates a latch-pulse-interleaved module. This circuit generates three interpolated sub-signals for time-over-threshold (TOT) and clock-period calibration (CAL) measurements. The interleaving strategy exploits the delay difference between a NAND gate in the ring oscillator delay line and a voltage-controlled inverter. Regulated by a delay-locked loop, the time interval between the sub-signals is maintained at one-third of the unit delay (Td/3). This architecture improves the final timing resolution to 7.5 ps, representing a three-fold enhancement over the previous version. Post-layout simulations indicate a stable bin size distribution, with differential non-linearity (DNL) and integral non-linearity (INL) confined within ±0.5 LSB and -0.6 to +0.2 LSB, respectively. At a 100-MHz event rate, the TDC core consumes 2 mW per channel and occupies an area of 419 × 134 µm². The ASIC has been taped out, and its specifications indicate applicability for large-scale, multi-channel readout systems in high-luminosity colliders.