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Description
In applications such as particle physics experiments, synchrotron radiation facilities, space exploration, and medical imaging, high-speed serial links are essential for data transmission between front-end and back-end systems. The development of high-performance clock data recovery (CDR) and phase-locked loop (PLL) circuits represents a key focus in the design of such systems. The proposed CEPC common front-end electronics requires a high-speed SerDes ASIC, capable of supporting an uplink data rate of 11.09 Gbps and a downlink data rate of 2.77 Gbps. This paper presents a dual-mode clocking circuit operating in either CDR or PLL mode. Both modes share a common voltage-controlled LC-tank oscillator covering two sub-bands, with a tuning range from 4.89 GHz to 5.96 GHz across all process, voltage, and temperature (PVT) variations. Mode switching is achieved by enabling the corresponding phase detector, charge pump, and low-pass filter. In PLL mode, the circuit receives a 43.33-MHz reference clock and synthesizes a 5.55-GHz output. In CDR mode, it accepts half-rate serial data at 2.77 Gbps and recovers both the data and synchronized clock signals (5.55 and 2.77 GHz). The generated clocks are distributed to the SerDes, clock dividers, and output drivers. The clocking circuit integrates 16 channels of clock dividers and multiplexers, with 9 channels brought out due to I/O constraints. Each channel offers seven selectable frequencies. The simulated core power consumption is approximately 38 mW. Fabricated in a 55-nm CMOS technology, the circuit is scheduled for testing in August, with detailed design and measurement results to be reported subsequently.