Speaker
Description
CIEMAT has lead the upgrade of the CMS DT electronics for HL-LHC upgrade, being in charge of fabricating both front end and backend electronics:
- The 180 OBDT-theta frontend boards host a Mircrosemi FPGA that can provide Multi-TDC (>200 channels) capability with a bin size requirement of <1 ns. They have been irradiated up to 100 Gy at the CHARM irradiation facility and operated in the CMS detector for several years. These boards are being assembled at 5 sites, including CIEMAT, in mechanical structures that also host the OBDT-phi boards, fabricated by INFN Padova, and cables interfacing to the chamber. Installation of these structures in CMS should happen during the first 2 years of Long Shutdown 3 (LS3) starting from September 2026 according to present schedule.
- On the backed, CIEMAT has developed and deployed in FW on the target FPGA (VU13P) the algorithm to reconstruct the muon segments in the chambers within a constrained allocated latency of ~ 1 us. It is also on charge of fabricating and testing half of the custom ATCA boards hosting the FPGAs. Three prototypes have been built and operated in CMS setups, including in setups receiving collision data from OBDT-thetas in the detector. Final production is expected in the second half of 2026.
Improving the use of timing information will be relevant for the next generation of particle physics detectors. One of the intrinsic aspects to achieve when using TDCs (Time to Digital Converters) is the quality and the low jitter of the clock. Thus, clock distribution becomes critical to ensure an optimal time measurement and this is usually done through a chain of FPGAs connected via optical serial links up to the highest acceptable radiation region in the experiment. Many detector components of planned e+e- colliders experiments share with LHC Muon detectors relatively low radiation scenarios and thus can enjoy the versatility of using newly available radiation tolerant FPGAs instead of ASICs for on detector electronics. CIEMAT is participating in DRD7.3 subgroup (timing) studying the timing performance, both in terms of precision and of phase-determinism of intrinsically rad-hard Microsemi FPGAs, a device we have developed significant know-how in the context of the CMS HL-LHC upgrade. Measurements of the timing stability will be presented as well as prospects to improve the TDC in FPGA from 0.8 ns required in CMS to O(50 ps).
The growing capacity of high-end FPGAs enables more powerful algorithms in high-energy physics backends both for triggering purposes and for efficient reconstruction in triggerless systems, but introduces new challenges for firmware developers, specially under fixed latency requirements. CIEMAT has presented several contributions on this area in DRD7.5 subgroup (COTS devices) and other development forums. The largest AMD devices, composed of multiple silicon dies (SLRs), face data transfer timing challenges due to Vivado’s placer limitations in large designs. In particular, pipelined buses crossing SLRs often experience poor flip-flop placement, impacting timing and latency. To deploy a complex Drift Tube AM alogorithm for the CMS HL-HHC upgrade, a 4D pseudo-linear fitter, an specific Python tool has been developed. It automatically generates optimized placement constraints for pipeline registers, equalizing propagation delays of the stages to improve timing closure while minimizing latency, number of pipeline stages, and resource utilization. This tool provides improved performance with respect to the native AMD/Xilinx existing software.