Speaker
Description
A 50 kt Iron CALorimeter (ICAL) has been proposed to study atmospheric neutrinos using Resistive Plate Chambers (RPCs) as the active detector elements. It’s proposed location is an underground cavern in a mountain, to reduce the cosmic muon background. A scaled down (1/600) version of the ICAL called the mini-ICAL has been constructed and is being operated at the IICHEP transit campus in Madurai, for the last few years, to study the construction and performance of the detector and ICAL electronics. The mini-ICAL comprises of a 4 m × 4 m × 1.1 m magnet made of 11 layers of iron plates interleaved with RPCs of size 2 m × 2 m in two stacks in the central region of a near uniform magnetic field. In order to study the feasibility of a shallow depth neutrino experiment a plastic scintillator based cosmic muon veto detector (CMVD) is being built around the mini-ICAL.
The CMVD needs to provide a muon detection efficiency of more than $99.99\%$ and false positive rate of less than $10^{-5}$. The CMVD consists of veto walls on three sides and the top of mini-ICAL. The veto walls are made from extruded plastic scintillator (EPS) strips. The top wall (the roof) will have four and the side walls will have three layers of EPS strips. Scintillators in different layers are staggered by 1/3 or 1/4 of the strip width to minimise any effect of the inter-strip gaps. The front side of the mini-ICAL won’t have a veto wall in order to provide access for the maintenance of the mini-ICAL. The EPS strips are 4.5, 4.6 or 4.7 m long and 50 mm wide, and have two holes separated by 25 mm, running along the full length of the strip. A wavelength shifting fibre of 1.4 mm diameter is inserted in each hole for light collection, and a Hamamatsu SiPM of an active area of 2 mm × 2 mm is mounted at both ends of the fibre for signal readout. A total of 760 EPS strips, 7 km of fibre and 3040 SiPMs will be used.
The SiPM signals are amplified by trans-impedance amplifiers (TIA) of gain 1200 ohm to produce a voltage pulse. A DRS4 ASIC based readout system is being designed to sample the SiPM signals at a rate of 1 GSa/s. The region of interest of the DRS4 is chosen so as to cover the SiPM’s entire signal profile in addition to accounting for the latency of the mini-ICAL trigger. The samples are digitised on receiving a mini-ICAL trigger, and zero suppressed data is transferred to the back-end data server. The mini-ICAL muon tracks are extrapolated to the CMVD and matched with the CMVD hits to evaluate the CMVD muon veto efficiency. An FPGA based DAQ board consisting of 40 TIAs, 5 DRS4 ASICs and a network interface chip is being designed. The board will also have an SiPM bias generator and SiPM calibration logic. 76 such boards will be required to readout the 3040 SiPMs.
This paper will discuss the design and construction of the CMVD and its readout.
| Session | Future Experiments and Detector Development |
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