Speaker
Description
The usage of FPGA-based DAQ systems has been growing in instrumentation and control systems for Big Science experiments over the last years. The combination of flexibility and performance that FPGAs give to DAQ and processing systems allow to apply them in multiple applications such as data acquisition, processing algorithms, complex timing and triggers mechanisms, interlock operations, and machine-learning applications. At present, three options exist to develop using FPGAs: hardware description languages (VHDL, Verilog/SystemVerilog), graphical languages like LabVIEW/FPGA; and high-level languages such as HLS languages or OpenCL. From these, HDLs are the most complex to use, but they offer the highest flexibility and control over the implementation, while not being bound to a particular hardware manufacturer. Alternatively, LabVIEW/FPGA is easier to use, but it is constrained to specific hardware devices. Lastly, HLS languages and OpenCL enormously simplify the hardware description using high-level languages like C/C++ which are also hardware agnostic. Additionally, standardization adds value to high-level languages, reducing the development times, to the extent that modules or complete software layers can be reused.
The work presented here is a set of methods and tools that allow developing applications for FPGA-based instruments in a standardized way, using the following elements: an OpenCL compliant Board Support Package for a PCIe device; an OpenCL interface to communicate with high-speed AD/DA converters using the JESD204B standard; a set of OpenCL Kernels to support common DAQ functionality, capable of acquiring and processing at high sampling rates; and a standardized software interface, including the Nominal Device Support software layer supported by ITER that integrates the whole solution with EPICS.
A discussion is provided on how this methodology simplifies integration and improves maintainability compared to other development languages and tools.
