Speaker
Dr
Gianluca Traversi
(University of Bergamo)
Description
This work aims at discussing the design criteria and the characterization results relevant to a novel kind of monolithic active pixel sensors (MAPS) in deep submicron CMOS technology (130nm minimum feature size) for vertexing applications at the ILC. Compared to other CMOS MAPS, such devices implement pixel-level data sparsification and time stamping, with similar functionalities as in hybrid pixel sensors. The deep n-well (DNW) available in this CMOS generation is used to collect the charge released in the substrate, and pixel signal processing is performed by a classical optimum amplifying stage for capacitive detectors. This approach has been validated by the first prototype chip (SDR0) containing different test structures of 25x25um2 pixels where both analog and digital functions have been integrated inside the elementary cell. A laser source has been used for the experimental characterization of the device properties in terms of charge diffusion among pixels. In the final paper, the experimental characterization of the prototype chip, including the calibration with soft X-rays (55Fe) and the response to beta-rays (90Sr), will be presented.
Author
Dr
Gianluca Traversi
(University of Bergamo)
