20–23 Oct 2026
University of Washington
America/Los_Angeles timezone

Learning MOSFET Models from I–V Data: A Neural Surrogate Approach Validated on the Open SKY130 Process

20 Oct 2026, 19:00
5m
University of Washington

University of Washington

Alder Hall, 1315 NE Campus Pkwy, Seattle, WA 98105
Poster RDC 4 Readout & ASICs Reception and Poster Session

Speaker

Nishan Niraula (University of Texas at Arlington)

Description

Front-end ASIC design for particle detectors requires device models that are accurate under the intended operating conditions. Applying foundry-calibrated compact models, including those available through open-source process design kits (PDK), beyond their characterized operating range, such as at cryogenic temperatures, requires further validation and, where necessary, refinement. We investigate a complementary, data-driven approach to modeling MOSFET DC characteristics without explicit extraction of compact-model parameters. Using simulated room temperature characteristics from the open-source SkyWater SKY130 PDK as a controlled benchmark, we train a residual neural network to predict drain current from gate width, gate length, and terminal biases. Derivative (Sobolev) supervision constrains the bias dependence of the predicted current, with accuracy evaluated for both drain current and transconductance. Across 15 MOSFET geometries excluded from training, the surrogate achieves a mean on-region current error of 1.3%, a mean threshold-voltage error of 1.8 mV, and a mean transconductance error of 3.6% relative to the reference simulations. Accuracy decreases at short channel lengths and near the boundaries of the sampled geometry range. We also apply the methodology to measured room temperature MOSFET characteristics, using 28 devices for training and testing and three additional devices held out for validation. The held-out devices were selected to include geometries both within and outside densely sampled regions of the training set, probing interpolation as well as generalization to new geometries. In preliminary results, median relative drain-current errors are 4–6% for two validation devices and 18% for the third. The highest-error device falls within a sparsely sampled gate-width interval, suggesting that limited geometry coverage may contribute to the reduced accuracy. Finally, we discuss our ongoing efforts to apply this approach to MOSFET characteristics measured by our group at 77 K and the challenges of modeling these cryogenic data.

Authors

Nishan Niraula (University of Texas at Arlington) ASHISH RIMAL (University of Texas at Arlington) Faith Beall (The University of Texas at Arlington) Olivia Seidel Yuan Mei (The University of Texas at Arlington) A.D McDonald ilker Parmaksiz (Rice University) Varghese Anto Chirayath (University of Texas at Arlington) Jonathan Asaadi (University of Texas at Arlington) J.B.R. Battat

Presentation materials