Speaker
Description
Future high-energy physics (HEP) experiments will require increasingly dense, low-noise and power-efficient readout systems capable of operating in extreme environments. Furthermore, these detectors will require an increasing number of functionalities, including, but not limited to power management, high-speed I/O, and low-noise analog front-end electronics. In 2019, the Office of Science published a report called the “Basic Research Needs for High Energy Physics Detector Research & Development” that proposed the development of verified System-on-Chip (SoC) IP for the different functionalities required, and creating a database of reusable IP for the HEP community. This approach, however, requires each functional block to be designed and tested for each technology node that detectors will be fabricated in, and all functional blocks cannot be implemented in its ideal technology node (e.g. a mature BiCMOS node for a low-noise analog front end and a cutting-edge CMOS node for digital logic), limiting system performance and efficiency. Furthermore, upgrading a single functional block in the detector requires the entire chip to be re-designed and re-tested. For these reasons, we believe that a System-in-Package (SiP) or “chiplet” based approach, where each functional block can be designed as a standalone die and integrated together on a common interposer, would be a viable method to create a database of verified, re-usable chiplet IP for the HEP community. The simplest implementation of this would be a passive silicon interposer which only contains routing for power and data. This would allow each functional block to be designed in a technology tailored to its function and allow designers to upgrade single functional blocks without requiring a re-design of the entire detector system.
In order to take advantage of these chiplet-based technologies for HEP applications, a common die-to-die (D2D) communication interface must be adopted. However, each die will require a power supply according to its technology node, so communication must occur between chips with varying ranges of power supply levels. While AC-coupling can alleviate this issue, it requires series capacitors that must be integrated on the chiplet, which can significantly increase area, or on the interposer, which would not available on passive interposers. Furthermore, encoding is required to reduce baseline wandering, which adds transceiver complexity. DC-coupled links, however, greatly simplify the link architecture and allow for the direct connection of the transmitter and receiver. This allows simple, compact, and high-speed transceiver designs that minimize latency and power consumption, which are essential for these D2D links to ensure SiP performance and efficiency remain high. For these reasons, we propose a standard, passive-interposer based transceiver architecture for D2D links, capable of VDD-agnostic communication. Upon startup, the connected transceivers run a common calibration procedure in which the power supply levels are compared, and the common power-supply level for each transceiver is set to the minimum value. This allows for reliable operation while maximizing the allowable swing, ensuring high signal integrity with minimal equalization required. The transceiver utilizes a single-ended voltage-mode architecture, minimizing the required area, and eliminating static power dissipation as opposed to current-mode solutions. The proposed system is verified in simulation for a 65 nm CMOS mode. The transceivers are designed to operate at 1.2V and 2.5V respectively at a data rate of 4 Gb/s for a passive silicon interposer channel reach up to 10 mm.