20–23 Oct 2026
University of Washington
America/Los_Angeles timezone

FEB2 Analog Performance for the ATLAS LAr Calorimeter: Bridging Performance to Design

20 Oct 2026, 19:05
5m
University of Washington

University of Washington

Alder Hall, 1315 NE Campus Pkwy, Seattle, WA 98105
Poster RDC 4 Readout & ASICs Reception and Poster Session

Speaker

Rui Xu (Columbia University (US))

Description

The higher proton-proton collision rates of the CERN High-Luminosity Large Hadron Collider (HL-LHC) requires a full replacement of the ATLAS liquid argon (LAr) calorimeter precision readout electronics. The updated LAr frontend readout system is implemented on the Frontend Board 2 (FEB2) that conditions and digitizes 128 calorimeter channels using a collection of radiation-tolerant ASICs custom-designed for this purpose. In addition to analog performance and radiation tolerance requirements over a life expectancy of 20 years, the FEB2 board and the ASICs are designed with scalability as a first-order requirement, with 1524 FEB2 boards needing to be installed to cover the almost 200k LAr calorimeter channels to be read out. Each channel is amplified, split into two overlapping gain scales, and shaped before both gain scales are digitized with 15-bits of granularity at 40 MSPS and streamed off-detector in real time without buffering. The FEB2 performance has been validated to meet the challenging specifications in a ~1%-scale system test across multiple boards inside a mock front-end crate (FEC). The measured equivalent noise current (ENI) is dominated by the input-referred noise of the preamplifier/shaper ASIC which operates at room temperature. Coherent noise between channels is measured to be about 1.2% of the total noise when measured over around 1500 channels, and the coherent noise scales sub-linearly with the addition of more channels. In response to LAr-shaped calibration pulses, the FEB2 achieves <0.1% energy resolution and <100 ps time resolution for large pulses. Long-term stability tests were also performed in the FEC. This presentation focuses on the design decisions at the ASIC, chipset interface, PCB, and architecture level, that were implemented to achieve these results. Lastly, we also discuss specific lessons learned and design revisions done to improve these performance metrics across multiple design iterations.

Author

Rui Xu (Columbia University (US))

Presentation materials

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