Speaker
Description
We present the design of the first prototype from this program: a waveform-sampling ASIC in the open-source GF180MCU process, modeled on the IRSX digitizer of the Belle II TOP detector. The program is introduced in a companion talk. The prototype targets the 'wafer.space' GF180MCU shuttle (GDS due December 2026) and is a reduced-scale demonstrator. The test chip has one channel of four sampling cells, each with its own hold capacitor and comparator, and the cells share a ramp generator and a Gray-coded counter. All four samples are digitized in parallel with 8-bit Wilkinson capture. The design utilizes an AI-assisted, human-in-the-loop workflow based on open-source tools for circuit design, layout, and verification.
Unlike the IRSX, the cells use bottom-plate sampling. The sampled input and ramp voltage drive the top plate of the hold capacitor through dedicated switches, whereas the bottom plate connects to a constant reference voltage through a switch and feeds the comparator directly. This configuration maintains a fixed-threshold comparator decision and makes charge injection independent of the input voltage, eliminating signal-dependent distortion and leaving only a constant pedestal. We will discuss the sampling scheme, the choice of hold capacitor, comparator, simulation results across PVT and mismatch, digital-on-top integration of analog blocks, and the current status toward tape-out.