Speaker
Description
Real-time trigger systems must sustain high-throughput readout while meeting strict timing requirements for control signals. We present a scalable streaming readout architecture for a large-scale FPGA-based global trigger system with over 100 nodes, each implemented on an AMD Versal device. Each node includes readout firmware that integrates a 9.6 Gbps ingress link for trigger and timing distribution and a 25.78125 Gbps egress link for selected event data transmission, forming a distributed readout network. This system reduces the 40 MHz input collision rate to approximately 1 MHz through distributed trigger selection, requiring efficient event buffering, selection, and aggregation across nodes. The design separates a timing-critical control path from a high-throughput data path and employs pipelined streaming and derandomizing buffers to support scalable and burst-tolerant readout. This approach enables scalable, high-throughput readout while preserving the timing constraints required by real-time trigger systems.