Speaker
Description
To achieve instantaneous luminosities 5-7.5 times of the nominal value of the LHC, it poses significant challenges to the Trigger and Data Acquisition systems during HL-LHC upgrade. A baseline architecture has been chosen for the ATLAS Phase-II upgrade, relying on a single-level hardware trigger. The Global Trigger performs complex algorithms on full-granularity calorimeter data. The Global Trigger is divided into three sublayers: the Multiplexer Processor (MUX), the Global Event Processor (GEP), and the Global to Central Trigger Processor interface (GCI). The MUX collects data from detectors (calorimeter and muon) and legacy Feature Extractor modules, time-multiplexes them bunch-crossing by bunch-crossing and sends full events to the GEP layer in a round-robin fashion. Each GEP node receives the full event data pertaining to a particular bunch-crossing, executes complex algorithms, and sends the results to the GCI, which comprises a single node that selects and resynchronizes the results from all GEP nodes before sending them to the Central Trigger Processor (CTP). In total four hardware prototypes have been designed since 2019, now the full-function Global Common Module (GCM) hardware prototype v4 based on Versal premium FPGAs and 25Gb/s optical modules have been designed to fulfill the requirements and is used for the firmware development and slice test. Details of all the prototypes design will be presented at this meeting.