Speaker
Description
The ATLAS experiment is currently preparing for the High Luminosity LHC era, scheduled to begin in a few years time with the start of run 4. ATLAS will be upgraded to support at least 200 simultaneous proton-proton interactions per bunch crossing. As part of these upgrades, the trigger system is also being upgraded to support a 10x increase in readout rate, and-- for the first time-- a dedicated tracking subsystem as part of the second-stage Event Filter trigger. The Event Filter will receive data from the entire detector at 1 MHz and need to output events at a rate of 10 KHz; due to high pileup conditions, efficiently reconstructing tracks and vertices can provide a major improvement in determining whether to accept or reject events of potential interest. A number of possible Event Filter Tracking designs are currently under study, with a final decision on the system architecture expected by next year, but due to power and latency concerns, there is significant interest in "accelerator" options, where a FPGA (or GPU) serves as a tracking co-processor for the CPU based Event Filter cluster. In this talk, I will discuss some of the studies ongoing towards FPGA-based EF tracking solutions, with a particular focus on ways to efficiently reject fake tracks on the FPGA itself, such as fast linearized fits or neural network-based methods.
