Speaker
Description
The advent of diffraction limited storage ring synchrotron facilities is pushing the requirements of X-ray detectors into a new regime. The Diamond II synchrotron will deliver X-ray fluxes ~10$^{12}$ ph/mm$^2$/s at the detector for some experiments. At such high fluxes the photons arrive at such a rate that conventional photon counting detectors are unable to make accurate measurements. Additionally, the energy of the X-rays will increase to above 20keV on many of the beamlines and the traditional Si detector technology becomes transparent. STFC have developed the DynamiX ASIC to readout CdZnTe detector material to offer a solution to the requirements of 4th generation synchrotrons.
A test structure has been manufactured in a 65nm CMOS process with 16x16 pixels on a 110µm pitch. The concept is designed to be scaled up to 192 x 192 pixels in future versions. The ASIC achieves a high dynamic range by operating at a frame rate of 533kHz, to match one orbit of Diamond, and an integrating amplifier with two stages of charge cancellation and digitisation in each pixel. The first “coarse stage” is optimised to cancel 25 photons at 25 keV at a cancellation rate of 166MHz and an 8-bit counter that records each cancellation. The remaining signal charge at the end of a frame is passed to the “fine stage” that conducts a constant rate charge removal that is timed by an 83MHz clock. A charge equivalent to 0.2 of 25keV photon is removed for each clock count and a 7bit counter records the magnitude of the charge. An out-of-range bit is used to identify coarse stage transfers greater than 25 photons. Each 4-column wide block of pixels is readout as 64b66b Aurora encoding data using a 14.1Gbps CML serialiser. The test structure and plans to scale up the technology will be presented.
| Your name | Matt Wilson |
|---|---|
| Institute | UKRI STFC |
| Email address | Matt.Wilson@stfc.ac.uk |
