26 February 2026
University of Applied Sciences Wiener Neustadt
Europe/Zurich timezone

What to Expect

  • Introduction to FPGA-based design using Lattice Radiant
  • RTL-based development (VHDL / Verilog)
  • System-level concepts using Lattice Propel
  • Hands-on labs using MachXO4 evaluation boards
  • Outlook on how the same design flow scales toward more robust, space-oriented platforms (e.g. Avant™)

 

Practical Information

  • Target level: zero to low prior FPGA knowledge
  • Hardware: MachXO4 evaluation boards provided by Lattice
  • What to bring: your own laptop + USB-C cable
  • Language: English (informal support in German possible)

 

Conference information

Date/Time

Starts

Ends

All times are in Europe/Zurich

Location

University of Applied Sciences Wiener Neustadt
Seminar room 07 (1st floor)
Johannes Gutenberg Str. 3 2700 Wiener Neustadt
Registration
Registration for this event is currently open.