Speaker
Description
Coplanar waveguides (CPWs) are used ubiquitously for microwave signal transmission in superconducting quantum processors, and air bridges are crucial to maintain signal hygiene and enable high-density, space-efficient routing. While their use in quantum processors to maintain ground connections across complex circuit topologies is well established empirically (Janzen et al., 2022, and related works), their impact on quantum device performance has not been studied very quantitatively or systematically. In addition, cleanroom process flows and outcomes are often highly facility-specific, necessitating the development of air-bridge nanofabrication recipes for local cleanrooms.
Here, we use electromagnetic modelling to explore how physical fabrication constraints impact the electromagnetic (EM) performance of both air bridges and their host devices, focussing on suppressing slot-line modes emerging during signal transmission along CPWs. We also develop a nanofabrication method to construct aluminium air bridges on a Tantalum thin film (similar to both Chen et al., 2013, and Bu et al., 2025), using the tools and materials available at the University of Sydney Research and Prototype Foundry (using lithography, evaporative deposition and lift-off techniques to define bridge width, thickness, and height).
Our EM modelling is carried out using ANSYS HFSS, including EM mode analysis and full-wave 3D simulations of representative CPW sections. Informed by our parallel nanofabrication work, we vary air-bridge geometry and placement density and evaluate scattering parameters over the operating band to quantify microwave reflections and scattering loss. We then study how air bridges impact the performance of specific on-chip design features like CPW bends and high-Q resonators. Using these results, we optimise air-bridge performance under practical constraints imposed by nanofabrication processes and sample-holder design, identifying parameter windows that meet impedance matching and microwave scattering loss targets. This in turn informs our fabrication recipe, which is designed to be transferable to a wide range of superconducting processor layouts.
