Author: Forest

Reduction of Multiple Triggering in Counting Detectors
Dr. X. Zhu, Dr. D. P. Langstaff*
Institute of Mathematics and Physics, Aberystwyth University
* Corresponding author: Tel.: +44 (0)1970-622838; fax: +44(0)1970-622826; e-mail: dpl@aber.ac.uk

Introduction:
Position sensitive detectors (PSD) have become increasingly important in mass spectrometry and other applications as they allow spatial information to be recovered as well as information on the number of particles. Multi-anode detectors are conceptually the simplest imaging devices employed with microchannel plates (MCPs). In detectors utilising MCPs as an amplification stage, there is always a degree of charge cloud spreading within the MCP stack and also between the MCP stack and the readout device. This charge cloud spreading results multiple triggering within event counting detectors, leading to degradation of spatial resolution and statistical noise on the resultant spectrum.
We present a scheme based on a synchroniser in conjunction with a multi anode structure to minimize multiple triggering.

Chip configuration:
A “first-past-the-post” voting circuit interposed between the charge amplifiers/discriminators and the counters rejects multiple triggering and gives true event counting in the detector.
A. Principle
The basic principle of operation of the synchroniser relies on the fact that the collection anode nearest the centre of the charge cloud emanating from the MCP will receive more electrons that its neighbours and consequently reach the switching threshold first. The synchronizer is arranged that when a particular channel triggers, its signal is allowed through to the appropriate counter, while at the same time an inhibition signal is generated which prevents the output of the neighbouring channels from reaching their counters.
Fig.1 Collection anode and sensor amplifier

B. Design of synchroniser
As can be seen from Fig. 2, the synchroniser block is formed from a number of 3-input circuits, tiled together such that each 3-input circuit receives inputs from its associated pixel and its 2 immediate neighbours. 1- and 2- input ‘dummy’ circuits are used at the edges of the array to ensure that the parasitic capacitances are kept as equal as possible for all inputs to the synchronizer block.
Fig.2 Floor plan of the synchroniser
The schematic of single three-input synchroniser constructed from cross-coupled three-input NAND gates is illustrated in Fig. 3. The inputs to the synchroniser pass through the circuit on a metal layer, facilitating tiling the blocks together. The dummies are shown in Fig.4.
Fig.3 3-input synchroniser Fig.4 2 and 1-input dummy

C. Layout
A portion of the layout of the detector IC incorporating the synchroniser is shown in Fig.5. The amplifier/discriminator circuits are at the bottom of the layout, with the pitch of the synchroniser circuit arranged to match. As the sense of the synchroniser inverts the logic signals as they pass through it, an inverter stage is added to the output of each amplifier/discriminator block.
Fig.5 Layout of IC

Counters

Synchronisers

Amplifier/Discriminators

D. Simulations
Simulations were performed using the T-Spice simulator. Simulations were first performed on the circuit after transistor level schematic design and then again after layout using extracted values for parasitic capacitance. The MCP was simulated by assuming that the output was a triangular current pulse with rise time of 150ps and a fall time of 550ps. The peak amplitude of the current pulse was calculated from the total charge within it (MCP plate gain), the time over which the charge arrived and the distribution of the charge over a number of electrodes. In order to determine the range of MCP gains over which successful operation could be expected, simulations were performed assuming that the adjacent channel received 95% of the charge arriving on the channel of interest. Under these conditions, the synchroniser was shown to work with over a range of plate gains from 2.5×106 to 5×107. typical simulation results are shown in Fig.6. The simulated delay time versus plate gain is shown in Fig.7.

Fig.6 Simulation of Counter and synchroniser	Fig.7 Simulated plate gain versus delay time

Conclusions:
The ASIC has been designed and post layout simulation based on AMI 0.5um CMOS process has been conducted. The simulation results have shown that the detector and synchroniser can work over a large range of signals. The measurement results will be conducted after the chip is fabricated in October 2008.
The final device comprises some 192 3-input synchronisers and 16-bit ripple counters with tri-state outputs, 195 shift register elements, 24 tri-state buffers and other support circuitry. The device count is approximately 130,000 transistors which, gives an overall silicon die size of 7mm×5mm including the collection anodes.

Acknowledgements:
The authors acknowledge support from the Welsh Assembly Government under the Patent Proof of Concept programme of the Knowledge Enterprise Fund.